`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    09:54:49 10/31/2012 
// Design Name: 
// Module Name:    SQUARE_UNIT 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module SQUARE_UNIT #(parameter WIDTH=16)
(

    input clk,
    input rst,
	 input signed [WIDTH-1:0] a_r,
    input signed [WIDTH-1:0] a_i,
    output reg signed[WIDTH+WIDTH+1-1:0] out
	 
    );
	 
	always@(posedge clk or negedge rst)
	if(!rst)
		out <= 0;
	else
		out <= a_r*a_r+a_i*a_i;

endmodule
